1. Field of the Invention
The present invention relates generally to integrated circuits, and more specifically to a multiple level magnitude comparator circuit.
2. Description of the Prior Art
Magnitude comparator circuits are used when it is necessary to determine the relationship between the magnitude of two numbers--whether a number is equal to, less than, or greater than another number in magnitude. Such circuits find a wide variety of uses in the electronics industry. For example, magnitude comparators are used in conjunction with subtractors to generate high speed flag logic for FIFO (First In First Out) memories. Magnitude comparator circuits are also used in arithmetic logic units (ALU's) found in personal computers (PCs) and other computers and by microprocessors for the execution of certain instructions.
Serial magnitude comparators are a common form of comparator circuits in the prior art. They have a number of individual bit comparators that together serially determine the magnitude of a number relative to another number. First, the least significant bits (LSBs) of the two numbers are compared before comparing the next bits, the LSB+1. This process continues serially until the most significant bits (MSBs) have been compared. The serial process can be quite consuming; at least 16 gate delays will be incurred for comparing two 16 bit words.
The individual bit comparators which comprise a serial magnitude comparator have four inputs: two inputs determined by the two bits to be compared, an input from the compare output of the previous magnitude comparator, and an input equal to the first bit of the two bits being compared. The compare output of a bit comparator is input to the subsequent bit comparator and reflects whether the magnitude of one bit is equal to, less than, or greater than the magnitude of the second bit. If the two bits being compared are equal, then the compare input is passed through the bit comparator as the compare output. If, however, the two bits are unequal in magnitude, then the input equal to the first bit of the two bits being compared is passed through as the compare output. This comparison process starts with the least significant bit (LSB) comparator and continues until the most significant bit (MSB) comparator finishes its comparison operation. The bit comparator with the highest order bit of difference determines the state of the final compare output.
The gate delays associated with serial magnitude comparators can have an adverse effect on overall system performance. This is especially the case when the magnitude of two large binary numbers must be determined. Several technologies, such as processors, video chips, image processing, and content addressable memories (CAMs), process large amounts of data and therefore compare large binary numbers. A fundamental way to enhance the speed at which FIFO flag logic is generated is to minimize propagation and gate delays associated with serial magnitude comparators. This approach is equally valid for those applications which compare large binary numbers. It would be desirable to accomplish this using current magnitude comparator design.